1. Technical Field
The present invention relates to a reconfigurable system, such as a programmable logic device, configured to provide communication between different modules.
2. Related Art
Reconfigurable systems, such as FPGAs, have traditionally been used as off-the-shelf replacements for Application Specific Integrated Circuits (ASICs), or as customizable versions of Application Specific Standard Products (ASSPs). As opposed to ASICs or ASSPs, programmability enables FPGAs to be purchased by customers and configured to provide a desired circuit. The FPGAs are further reconfigurable allowing reprogramming after startup. Reconfigurability allows FPGAs, for example, to be used for software-defined radios that have circuitry controlling their frequencies updated as the radio location changes. As another example, decryption algorithms have their keys and decoding circuits updated over time.
A block diagram of components of a conventional FPGA is shown in FIG. 1. The FPGA includes input/output (I/O) blocks 2 (each labeled 10) located around the perimeter of the FPGA, multi-gigabit transceivers (MGT) 4 interspersed with the I/O blocks 2, configurable logic blocks 6 (each labeled CLB) arranged in an array, block random access memory 8 (each labeled BRAM) interspersed with the CLBs, configuration logic 12, configuration interface 14, on-chip processor 16 and an internal configuration access port (ICAP) 20. The FPGA also includes other elements, such as a programmable interconnect structure and a configuration memory array, which are not illustrated in FIG. 1. Although FIG. 1 shows a relatively small number of I/O blocks 2, CLBs 6 and block RAMs 8 for illustration purposes, it is understood that an FPGA typically includes many more of these elements. Details of components of typical FPGAs are described in “Virtex-II™ Pro, Platform FPGA Handbook”, (Oct. 14, 2002) available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, incorporated herein by reference.
In general, the FPGA of FIG. 1 is configured in response to a set of configuration data values that are loaded into a configuration memory array of the FPGA from an external store via configuration interface 14 and configuration logic 12. External configuration interface 14 can be, for example, a parallel select map interface, a JTAG interface, or a master-serial interface. The configuration memory array can be visualized as a rectangular array of bits. The bits are grouped into frames that are one-bit wide words that extend in columns from the top of the array to the bottom. For that reason only a complete column can be reconfigured. A frame is typically defined as the smallest part of the configuration memory array that can be written to or read from. The configuration data values are typically loaded into the configuration memory array one frame at a time from the external store via the configuration interface 14.
The FPGA can be reconfigured by rewriting data in the configuration memory array. In one reconfiguration method, the ICAP 20 is used to rewrite data in the configuration memory array in order to generate or instantiate the FPGA's internal logic (e.g., CLB's 6 and BRAMs 8). In other words, one part of the configured FPGA can reconfigure another part of the FPGA. Without using the ICAP, reconfiguration is performed by loading reconfiguration frames through the configuration interface 14 using external customized logic components to over-write frame data in the configuration memory array.
More efficient reconfiguration of an FPGA is performed by only rewriting a portion of the frames or columns in the configuration memory array that need to be changed, a process known as partial reconfiguration. One way to enable an FPGA to take advantage of partial reconfiguration is to have the FPGA partitioned into physically separate modules. Each module provides circuit resources for implementing a task, i.e. an algorithm. As the processing requirements change, one or more of the modules are updated only to a degree necessary to perform a new algorithm. Similarly, smaller manipulations of a module can be made such as a change in inputs and outputs. Because the underlying FPGA fabric is SRAM-based, modules can be updated indefinitely. Because modifications to the algorithms performed by a module typically require modification of only a portion of the frames in the configuration memory, efficient operation can result using partial reconfiguration.
In order to provide for efficient partial reconfiguration, a circuit arrangement shown in FIG. 2 is provided. To control reading and writing of data into the configuration memory array 30 of an FPGA, a controller 32 is used. For self-reconfiguration, the controller 32 is included with the ICAP 20 internal to the FPGA. For externally controlled reconfiguration, as opposed to self-reconfiguration, the controller 32 is provided outside the FPGA. To mirror data in the configuration memory array 30, configuration store 34 is used, enabling faster data reading and writing. The configuration store 34 speeds read and write operations because a bottleneck is otherwise created through the configuration interface 14 to the configuration memory array 30. Configuration interface 14 is a slow interface. With the configuration store 34 used, data is first modified in the configuration store 34 and later loaded into the configuration memory array 30 through the configuration interface 14 in a frame-by-frame manner. For partial reconfiguration, only the modified frames are loaded from the configuration store 34 and then written by the controller 32 into the configuration memory array 30 of the FPGA.
In a further embodiment for partial reconfiguration, the modification store 36 is added. The modification store 36 includes information identifying physical resources to be modified and the state to which they will be modified. As opposed to the configuration store 34, the controller 32 can read and modify portions of frames in the configuration store 34 using the modification store 36 as a reference, rather than being required to modify entire frames significantly reducing modification time.
Dynamic reconfiguration is a form of reconfiguration used to enable rapid updating of the configuration memory. Dynamic reconfiguration involves the active FPGA being fully or partially reconfigured to update algorithms, parameters or connections while concurrently enabling operation of active circuits not being changed. With dynamic reconfiguration, modules are programmed into the FPGA and when some of the modules need reconfiguring to update the tasks, i.e. algorithms implemented by some modules, other modules can continue operation.
To enable the reconfigurable modules to communicate, a network is typically placed in the FPGA for access by the modules. In one system, a packet based network system is formed. With a packet network, modules share access to the common communication network. The network physical layer (or circuitry enabling communication) is a shared resource between all the modules. In another system, a bus network is instantiated between modules. Like the physical layer of the packet network, the physical layer of the bus is shared by all of the modules, and each module must wait for the bus or physical communications layer to be relinquished.
A reconfigurable task based system programmed into an FPGA to implement a Digital Signal Processor (DSP) system has been provided by Interuniversity Micro-Electronics Center (IMEC), a research center in Belgium. To enable task communication, IMEC implemented an on-chip packet based network. Although the network enables high bandwidth communication, communication speed is limited because the module tasks share access to a common network. The physical layer can only be accessed by a limited number of modules transmitting data at one time. As congestion builds, data must be buffered and tasks must wait to transmit and receive data.
The University of Karlsruhe of Germany has implemented a reconfigurable task based system in an FPGA programmed to implement multiple control functions. Modern automobiles have numerous microprocessors for controlling systems like windows, wiper blades, and moon-roofs. The University of Karlsruhe system brings all of the control functions performed by microprocessors onto one FPGA. Because the microprocessors are not all required to function at the same time, their functions can be time swapped into FPGA modules using dynamic partial reconfiguration. To enable communication between a main control processor and the logic implementing microprocessor functions instantiated in the modules, a bus network is provided between them. Like the packet network, the physical layer of the bus network is shared by all of the modules, and each module must wait for the bus to be relinquished by other modules before transmitting its data.